A hardware approach to reconfigurable lossless real-time tracer
Hua Si-liang, Lei Shi, Pang Jun, Tiejun Zhang, Donghui Wang, Hou Chao-huan · 2007
Address tracing at speed is essential to the debugging or analyzing software programs in a complex system. However, the generation rate and the size of real-time program traces are so huge that real-time program tracing is often infeasible without proper hardware support. In this paper, we present a reconfigurable lossless real-time tracer with three parts. A synthesizable RTL code for the proposed hardware is constructed and the tracer is integrated with a microprocessor. Hardware cost and speed is analyzed and typical programs are used to measure the compression results. The results show that the reconfigurable tracer is capable of real-time compression and outputting the compressed data less than 1 bit per cycle on average at 266 MHz with 172963 mum2area in 0.18 mum CMOS process.