Implementations of high throughput sequential and fully pipelined AES processors on FPGA
Chih‐Peng Fan, Jun-Kui Hwang · 2007
In this paper, we use FPGA chips to realize the highthroughput 128 bits AES cipher processor by new high-speed and hardware sharing functional blocks. The AES functional caculations include four transformation stages, which are SubBytes, ShiftRows, MixColumns and AddRoundKey. The content-addressable memory(CAM) based scheme is used to realize the new proposed high-speed SubBytes block. The new hardware sharing architecture is applied to implement the proposed high-speed MixColumns block. Then the efficient low-cost AddRoundKey architecture is used for real-time key generations. The utilized FPGA tool is Xilinx ISE™ 7.1 with XST™ synthesizer. In our proposed sequential AES design, the operational frequency can reach 75.3MHz and the throughput can be up to 0.876Gbits/s. In our full pipelined AES design, the operational frequency can process 250MHz and the throughput can be up to 32Gbits/s. Both of the proposed sequential and full pipelined AES realizations achieve higher throughput than the other sequential and full pipelined designs, individually.