AREA EFFICIENT IMPLEMENTATION OF ADAPTIVE FIR FILTER BASED ON DISTRIBUTED ARITHMETIC
Lisha Anna Daniel, Niji Mathews · 2015
Novel pipelined architectures for low-area implementation of adaptive FIR filter based on Distributed Arithmetic (DA) are proposed here. The designs perform parallel lookup table (LUT) update and concurrent implementation of filtering and weight-update operations. The conventional adder-based shift accumulation for DA- based inner-product computation is replaced by conditional signed carry-save accumulation in order to reduce delay and area complexity. The designs use fast bit clock for carry save accumulation but a much slower clock for all other operations. Look Up Table (LUT) size reduction techniques are employed within the filter structures. LUT techniques used include Offset Binary Coding (OBC) and Modified DA Technique, which are employed within the existing structure. Within the OBC technique, LUT structure employed is halved when compared to that of the existing designs. Smaller multiplexor is also used within this structure. Modified DA technique also employs half-sized LUT structure. For the latter technique, the filtering unit employs an additional adder structure but smaller multiplexor when compared with the existing designs. From synthesis results, it is found that the proposed structures are efficient in terms of area from the existing design.