Implementation and evaluation of AES/ADPCM on STP and FPGA with High-level Synthesis
Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro · 2015
Reconfigurable techniques are attract- ing attention as an alternative to dedicated hardware of SoC. We have evaluated FPGA and STP engine in order to confirm their performance whether they can substitute the dedicated hardware of SoC. We se- lected AES and ADPCM applications to compare the performance of FPGA and STP engine. The applica- tions were synthesized with the same high-level syn- thesis tools. Then, we implemented them onto FPGA and STP engine using the integrated development en- vironments. For the evaluation, we compared them in terms of resource usage, the number of states, the number of cycles, frequency, and execution time.