Implementation of decoders for symmetric low density parity check codes on parallel computation platforms using OpenCL
Andrew J. Maier, B.F. Cockburn · 2016
OpenCL is a high-level language that allows mixed hardware/software systems to be specified and compiled to run on heterogeneous parallel computing platforms. The hardware parallelism can take the form of multi-core central processing units (CPUs), massively parallel graphics processing units (GPUs), and, most recently, field-programmable gate array (FPGA) fabrics. OpenCL compilers for CPUs and GPUs have been available for over 6 years, but only recently has compiler support been extended to include FPGAs. This paper investigates OpenCL designs for the computationally demanding standard iterative decoding algorithm for low-density parity check (LDPC) codes. The LDPC decoding algorithm offers several kinds of potentially exploitable parallelism. Our objective was to investigate the design trade-offs in OpenCL that will produce the best performance when compiled by the Altera Offline Compiler (AOC v15.1) for OpenCL-to-FPGA. Within a relatively short design time we were able to implement a decoder that achieved 5.12 Mbps with a length-1024 (3,6)-regular code.