High speed UDP/IP ASIC design
Yi-Mao Hsiao, Ming‐Jen Chen, Kuo-Chang Huang, Yuan‐Sun Chu, Chingwei Yeh · 2009
With the growing of internet service, multimedia applications require higher communication speed. The network traffic has rapidly increased that produces amount of interrupts, memory copies and checksum calculation in end system. The CPU workload is heavy and the processing of network protocol task is the bottleneck. In this paper, we propose a UDP/IP ASIC to accelerate networking multimedia transmission. The checksum hardware just calculates packet header instead of whole packet with payload for UDP packet so that it can reduce the processing clock cycles for multimedia delivery. Besides, because of the Gigabit NIC support Jumbo Frame mostly, we figure out the packet size adopted 9 Kbyte from which the performance is higher than the traditional 1.5 KByte. As the results of simulation, the speed of the chip is 227.2 MHz and the area is 0.936 * 0.733 mm2. The power consumption without SRAM is 7.21 mW. Therefore, the system throughput achieves 7.11 Gbps that can deal with the traffic of Gigabit Ethernet in end system.