Design of a parametrizable low cost Ethernet MAC core for SoC solutions
Jose A. Moreno Zamora, P.J. Rodriguez Corrales, J.M. Sanchez Perez · 2004
This paper describes an efficient Ethernet medium access control (MAC) design, according to IEEE 802.3 standards for fast Ethernet (100 Mbps) a 10Base-T (10 Mbps) implementations in full and half duplex modes, suitable for re-use as intellectual property (IP) core in system-on-chip (SoC) designs. The description and contributed results exhibit that the main advantages of this design reside in a really low logic cost keeping a great tolerance for external clock frequencies and domains, and a high configurability and flexibility for master processors interface.