Generating all test patterns for stuck-at faults at a gate pole and their connection with the incompletely specified Boolean function of the corresponding subcircuit
Anzhela Yu. Matrosova, S. Ostanin, I. Kirienko · 2014
The algorithm of generating all test patterns for a stuck-at fault at a gate pole of single-output combinational circuit is suggested. It is based on the method of redefining products suggested before. It is known that a behavior of a subcircuit of a combinational circuit is presented by the incompletely specified Boolean function. It means that there are the input Boolean vectors of a circuit on which the value of the subcircuit output has no effect on the value of the circuit output. It is set up that the on-set vectors of a subcircuit incompletely specified Boolean function are represented by all test patterns for the stuck-at 0 fault at a subcircuit output and the off-set vectors are represented by all test patterns for the stuck-at 1 fault at the same output. This result may be used for structural combinational circuit minimizing and for partially programmable circuit design. The experimental results are presented.