Study of multigrain MRPSoC
V.S. Kavitha, K. V. Ramakrishanan · International Conference on Computing for Sustainable Global Development · 2016
There are several techniques to reconfigure the instruction set processors. One such technique is Multi Reconfigurable Instruction Set Processor System on Chip (MRPSoC). Integrating MRPSoC with multigrain parallelism for improvement of performance is done in this paper. By using MRPSoC, performance of the system is increased by 30%. Multimedia application computing can be accelerated by using multigrain parallelism. By implementing this integrated processor additional features can be added to MRPSoC. Multiple data is packed in a single register which forms a vector; this vector of multiple data is fetched to MRPSoC at a time. Since MRPSoC is a combination of MPSoC and RISP processor, instruction level parallelism can be achieved in MRPSoC. Once execution of operations in MRPSoC is complete, multiple outputs can be stored at different memory locations simultaneously. This paper is aimed to design MRPSoC interfaced with data level, instruction level and memory transfer level parallelism. Simulation results show a 30% improvement is completion time taken to execute a task and hence high speed computation can be achieved for all multimedia applications.