An automatic-power-save cache memory for low-power RISC processors
Y. Shimazaki, K. Ishibashi, K. Norisue, Susumu Narita, Kota Uchiyama, T. Nakazawa, I. Kudoh, R. Izawa, S. Yoshioka, Shozo Tamaki, S. Nagata, Ikuya Kawasaki, K. Kuroda · 2002
A test chip was fabricated using 0.5-/spl mu/m CMOS technology and the cache memory operated at 60 MHz with a supply voltage of 3.3 V, and it operated with a power dissipation of 8 mW with a supply voltage of 2.5 V at 10 MHz. Automatic-power-save architecture, a pulsed word technique and an isolated bit line technique reduced the power dissipation of the cache memory to almost 60% at a frequency of 60 MHz and to 20% at 10 MHz by these techniques.