Simulation environment to verify industrial communication circuits
Jaime Jiménez, Eduardo Fernández, José Luis Martín Martín, Unai Bidarte, Aitzol Zuloaga · 2003
In this paper a specific verification tool for digital communication circuits is presented. Applied to devices for the train communication network (TCN) and based on bit level exhaustive simulation, electronic designs in VHDL language can be validated before prototypes are produced. For this purpose, a virtual communication network is built by means of various TCN device models which interchange data. Such virtual nodes generate VHDL signals that simulate real traffic of master and slave frames. In this way, the VHDL description of a device which will be synthesised can be verified before configuring the FPGA.