Reconfigurable floating point adder
Vipin Gemini · 2014
Decimal floating point arithmetic is gaining importance because of its higher accuracy for financial, commercial and Web based applications. However, the binary floating point arithmetic is needed for scientific applications. Both these applications require general purpose processors (GPPs) for their execution. GPPs have separate hardware for decimal and binary floating point operations and therefore need a large area for their implementation. In this paper, we present a runtime reconfigurable floating point adder which targets both decimal and binary floating point addition on same hardware. The proposed design is 24.53% area efficient and approximately 7.6% faster than the previously reported designs. However, it is 6.3% slower for binary inputs.