A Low-cost BIST Scheme for ADC Testing
Yongsheng Wang, Wang Jin-xiang, Fengchang Lai, Yizheng Ye · 2006
A low-cost BIST scheme based on linear histogram for testing ADC is presented in this paper. A parallel time decomposition technique is presented to minimize not only hardware overhead but also testing time of the BIST scheme based on histogram. An area-efficient linear triangular waveform generator is discussed as test stimulus. The technique uses digital delta-sigma noise shaping to generate the on-chip precise analog stimulus and simplify the analog circuit of the generator at same time. A practical implementation is described and the performance is evaluated.