A configurable FFT Processor
Jing He, Ma Lanjuan, Xinyu Xu · 2010
In this paper, a configurable FFT processor is presented which can be configured as 8192 point, 4096 point, 2048 point and 1024 point FFT processor. The processor is based on mixed radix algorithm and single-path delay feedback(SDF) architecture is adopted. The configurable architecture is achieved by connecting or bypassing specific processing elements. To improve processor performance, a dynamic scaling approach is adopted and internal data is formatted as self-defined floating point, and the arithmetic for the self-defined floating point is simple. The experiment results show that the approach can achieve high and constant SNR. The processor is implemented on FPGA.