Area/delay driven NoC synthesis
Abir M'zah, Omar Hammami · 2011
The NoC synthesis defined as the generation of a Network On Chip (NoC) architecture optimized for a specific application subject to various constraints, is a very important step in ASIC design methodologies. In this work we will present a new NoC synthesis method based on linear programming. We will apply our algorithm on multimedia coregraphs like 263 enc MP3 dec, MPEG4 and H.264. We reduce the complexity of the problem by restricting possible connections between cores having common destination or origin edges. The obtained results give a free NoC topology which satisfies the required bandwidth and the maximum propagation delay time with an optimized area of the NoC.