A High-Speed, Low-Area Processor Array Architecture for Multiplication and Squaring over GF(2m)
Mohamed A. Fayed, Mohamed Watheq El-Kharashi, Fayez Gebali · 2007
We propose a novel, high-speed, low-area architecture for multiplication and squaring over GF(2m). The proposed architecture is processor array based, which utilizes the most significant bit multiplication algorithm and polynomial basis. A design space exploration to optimize the area and speed of the proposed architecture was done. Our architecture requires only m processing elements as compared to m2/2 for the best previous design. We use NIST-recommended polynomials, which makes our design secure and more suitable for cryptographic engines. The proposed architecture is implemented for m isin {163,283,571} on a Xilinx XC2V4000-6 device to verify its functionality and measure its performance. We achieve a frequency of 264 MHz, which allows the architecture to calculate GF(2163) multiplication in 640 ns and squaring in 57 ns.