Floating-Point Fused Multiply-Add Architectures
Eric Quinnell, Earl E. Swartzlander, Carl E. Lemonds · 2018 52nd Asilomar Conference on Signals, Systems, and Computers · 2007
Two new floating-point fused multiply-add architectures for the single instruction execution of (A times B) + C are presented. The three-path architecture uses parallel hardware paths similar to those in dual-path floating-point adders. The new bridge architecture re-uses common floating-point components to add a fused multiply-add instruction. Each new architecture as well as a collection of floating-point arithmetic units and a classic fused multiplier-adder have been designed using the advanced micro devices 65 nanometer silicon on insulator CMOS technology to fairly compare the new architectures.