MuCCRA chips: Configurable dynamically-reconfigurable processors
Hideharu Amano, Yohei Hasegawa, Satoshi Tsutsumi, Takuro Nakamura, Takashi Nishimura, Vasutan Tanbunheng, A. Parimala, Toru Sano, Masaru Kato · 2007
Coarse grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine in System-On-Chips (SoCs). Evaluation results in recent researches revealed that the parameters of optimal processor array structure: granularity, functions, array size, context size and interconnection flexibility, are completely different for each application. That is, DRPAs should be configurable for target SoCs and applications. MuCCRA is a project for developing a DRPA generator which can generate RTL model, testing environment and programming environment for various types of DRPAs just by selecting the specific parameters. Here, two prototype chips MuCCRA-1 and MuCCRA-2 developed in the project are introduced and evaluated. MuCCRA-1 was implemented with Rohm’s 0.18um CMOS process mainly for multi-media applications, while MuCCRA-2 with ASPLA’s 90nm CMOS process was designed focusing on area optimization used as a cost-effective IP in multi-core SoCs.