A novel dynamic scheduling algorithm of data hazard for embedded processor
Jia-Jing Lu, Xiaofang Zhou, Junyu Wang · 2007
To solve the data hazard of embedded processor, this paper designs a dynamic scheduling algorithm to improve the pipeline efficiency, which only increases one single-instruction buffer and some combination logic. In FFT and FIR experiment, the algorithm leads to the decrease of the pipeline conflict to 100% and 75% respectively. There is 8.2% additional area of the whole processor.