DSP implementation and performances evaluation of 1D and 2D DWT using the lifting scheme
Ihsen Ben Hnia Gazzah, Chokri Souani, Kamel Besbes · 2008
This paper presents the implementation of a lifting scheme-based DWT architecture on a digital signal processor (DSP) (TMS320C6713) core and the simulation using MATLAB. The 5/3 and 9/7 wavelet filters used in JPEG 2000 are both implanted and executed by the DSP processor for comparisons. The algorithms proposed are optimized at source code level and memory usage. The execution time for performing both DWTs is measured for 1D and 2D-DWT for different number of level, depending on on-chip and off-chip memory.