Floating-Point Unit Processing Denormalized Numbers
Zheng Li, Hu He, Sun Yihe · 2006
A hardware structure of floating-point unit (FPU) is presented. Four operations are supported, including: multiply-add-fused (MAF) operation A + (BtimesC), division, square-root operation, and conversion between fixed-point and floating-point numbers. The whole architecture is fully compliant with the IEEE 754 standard. In the MAF unit, the throughput is one operation per cycle, and the instructions are executed in three pipeline stages. Besides, rounding and denormalized inputs and outputs can be one-fly processed with little additional latency introduced. Radix-4 SRT iteration algorithms for both divides and square-root operations are used. A standard cell implementation for single precision calculation based on SMIC 0.18 mum CMOS technology has achieved