SELF REFERENCED EDGE DETECTION FOR CMOS PWM TRANSCEIVER
K. Mounika, P. Chiranjeevi · IJITR International Journal of Innovative Technology and Research - IJITR International Journal of Innovative Technology and Research · 2016
Technique is used to implement the CMOS PWM Transceiver circuit is presented. In this paper, A Self Referenced Edge Detection technique is implemented to analyze a CMOS PWM Transceiver circuit, by comparing the rising edge that is self-delayed by about 0.5 T and the modulated falling edge in one carrier clock cycle. An Area-efficient and high robustness (against timing fluctuations) edge detection enabling PWM communication is achieved without requiring elaborate phase-locked loops. Self-referenced edge detection circuit has the capability of timing error measurement while changing the length of self delay element, adaptive data-rate optimization and delay-line calibration are realized. The measured results with a 65-nm CMOS prototype demonstrate a 2-bit PWM communication, high data rate (4Gbps), small peak to peak jitter(4.8ns), and high reliability (BER > 10−12) with small area occupation (540 μ m2) and with high RMS (1.3). For reliability improvement, error check and correction associated with intercycle edge detection is introduced and its effectiveness is verified by 2-bit PWM measurement.