Using an FPGA to accelerate pupil isolation in iris recognition
Jennifer L. Shafer, Hau Ngo, Robert W. Ives · 2010
Iris recognition is an important application in the Department of Defense and the Department of Homeland Security. An algorithm that is both accurate and fast in a hardware design that is small and transportable are crucial to the implementation of this tool. As part of an ongoing effort to meet these criteria, this paper improves a segment of the US Naval Academy's RED iris recognition algorithm, namely pupil isolation. We show a significant speed-up of pupil isolation by implementing this portion of the algorithm on a Field Programmable Gate Array (FPGA).