A VLSI implementation of parallel fast Fourier transform
André Vacher, M. Benkhebbab, Alain Guyot, T. Rousseau, A. Skaf · 2002
This paper presents the design of a VLSI circuit to perform the Fourier transform using on-line most-significant-digit-first arithmetic. First, the principles of the pipelined fast Fourier transform are recalled, and a folded pipeline is introduced. Then on-line operators and operator merging rules are used to design a cost effective butterfly operator. Finally a circuit with 8 butterflies is described and compared to other realizations.>