A novel gate-offset NAND cell (GOC-NAND) technology suitable for high-density and low-voltage-operation flash memories
Shin-ichi SATOH, Toshio Nakamura, K. Shimizu, Kazuhiro Takeuchi, Hirohisa Iizuka, S. Aritome, R. Shirota · 2003
This paper describes a novel scaled and low-voltage-operation NAND EEPROM technology with a G_ate-O_ffset NAND C_ell (GOC-NAND), which is free from program disturbance in a self-boosted program. In GOC-NAND, novel source/drain engineering is introduced for the first time. The program disturbance is decreased by two decades of magnitude in 0.1 /spl mu/m generation, without area penalty and additional process steps. Furthermore, the program disturbance is not increased by scaling and low voltage operation. Therefore, GOC-NAND is indispensable technology for gigabit-scaled NAND EEPROMs.