OpenDSP in Xilinx FPGA
A.J. Salim, Masuri Othman, M.A.M. Ali · 2006
This paper describes the implementation of a 16-bit fixed-point DSP chip using the Xilinx Virtex-II FPGA. The design uses the modified IP core (OpenDSP) integrated with RAM and ROM in one FPGA chip. The chip is designed for small general-purpose applications. In order to verify the functionality of the chip, the FFT and IFFT algorithms were developed, implemented and tested to successfully work at a typical clock speed of 40 MHz and up to a maximum of 80 MHz.