Efficient rendering and cache replacement mechanisms for hierarchical tiling in mobile GPUs
Chih-Chieh Hsiao, Slo‐Li Chu, Shang-Shun Dai · 2012
The 3D rendering capabilities are now widely available in the consumer electronics devices because the consumer applications usually use it for superior user experience. However, those rendering capabilities have been very limited because the resources of these devices are limited; small amounts of memory, less bandwidth, and limited energy consumption. Therefore, the tile-based rendering becomes prevalent in mobile GPUs for consumer electronic devices. In the tiled systems, a hierarchical tiling technique is used to further reduce bandwidth requirement. However, the hierarchical tiling has very high locality when multi-core GPUs are adopted which is not well exploited. Therefore, this paper proposes a block-based rendering sequence and a multi-core locality-aware cache replacement (MLCR) mechanism to utilize this locality. The results show the proposed mechanism reduces cache miss rates from 46.78% to 38.06% when block-based rendering sequence is used with conventional cache replacement. The miss rate can be further reduced to 35.98% when incorporate proposed sequence with MLCR. Furthermore, the implementation cost is analyzed and shows the proposed mechanism is affordable in a consumer electronics device and improves performance of consumer applications with 3D graphics.