Optimized FPGA-based DDR2 SDRAM controller
Jian Qituo, Liu Liansheng, Yu Peng, Liu Datong · 2013
With the development of embedded systems, more and more applications require large and high speed memory. The FPGA-based solution also faces the same demand. Design and realization of an external storage with large capacity and high throughput in the FPGA-based embedded system is becoming a challenge. To satisfy the practical requirement, a DDR2 controller design is proposed, which efficiently and selectively integrates with the Altera DDR2 SDRAM High Performance Controller (HPC) module. Finally, the optimized DDR2 SDRAM controller based on Altera HPC is realized, and the goal that data accesses for DDR2 SDRAM with the ability of increase channel and relatively huge burst size is achieved. The optimized DDR2 controller has been implemented and verified in the Altera EP2SGX90E FPGA, and revealed a significant improvement in the performance compared with the individual HPC module. The experimental results show that this optimized DDR2 SDRAM controller demonstrates the properties of multichannel and high bandwidth memory access.