An efficient ASIC implementation of SHA-1 engine for TPM
Mingyan Yu, Tong Zhou, Wang Jin-xiang, Yizheng Ye · 2005
With the development of trusted computing systems, TCG promotes TPM as the core hardware building block. The SHA-1 engine in TPM contributes the performance of the whole platform. In this paper, the data flow latencies of the SHA-1 hardware implementation are analyzed, and the bottlenecks are optimized by special arithmetic structures. As a result, the frequency of the optimized structure has increased by 43%. And the performance of this SHA-1 engine is also compared with other SHA-1 engines by frequency, area and throughput.