FPGA implementation of CCSDS BCH (63, 56) for satellite communication
S. Arunkumar, T. Kalaivani · 2012
This paper considers the implementation of error detection and correction system for satellite communication on a FPGA (Field Programmable Gate Array) as per the protocols specified by CCSDS (Consultative Committee for Space Data Systems). BCH (Bose-Chaudhri-Hocquenghem) codes are cyclic codes that are capable of correcting multiple errors occurring in transmission. The implemented logic BCH (63, 56) is capable of correcting 1 bit error and detecting up to 2 bit errors. If the received command is not correctable, then erroneous authentication is prevented providing high probability of correct command execution. The algorithm is implemented in Cyclone II EP2C20F484C7 FPGA. Programming on a FPGA is easy, reliable and well suited for small sized satellites. The results show that the algorithm works quite well; any 2 bit error in any position of 63 bits was detected and 1 bit error was corrected. Simulation results in MATLAB and ModelSim are presented in detail.