Two systolic architectures for multiplication in GF (2m)
Wen‐Chou Tsai, Sheng‐Jyh Wang · IEE Proceedings - Computers and Digital Techniques · 2000
Two new systolic architectures are presented for multiplications in the finite field GF(2m). These two architectures are based on the standard basis representation. In Architecture-I, the authors attempt to speed up the operation by using a new partitioning scheme for the basic cell in a straightforward systolic architecture to shorten the clock cycle period. In Architecture-II, they eliminate the one clock cycle gap between iterations by pairing off the cells of Architecture-I. They compare their architectures with previously proposed systolic architectures and a semi-systolic architecture, and show that their Architecture-I offers the highest speed and Architecture-II the lowest hardware complexity.