The new test wrapper design for core testing in packet-switched micro-network on chip
Babak Aghaei, Shahram Babaie · 2009
Recent advances in packet-switched micro-network on chip arise great challenges in test and testability issues. This paper presents a novel test wrapper design for embedded cores in NoC. This wrapper uses functional ports for test data transmission. We assembled proposed test wrapper on a processor during hierarchical simulation. Clearly, simulation results show our proposed wrapper works correctly.