Fault Tolerant Deadlock-Free Adaptive Routing Algorithms for Hexagonal Networks-on-Chip
Sadia Moriam, Gerhard Paul Fettweis · 2016
Technology scaling has allowed the integration of a large number of cores on a single chip, which significantly improves the speed of on-chip processing. Network-on-chip is the interconnection network which provides efficient and flexible communication between cores in such multi-processor systems-on-chip. However, the performance enhancements of technology scaling come at the cost of reliability as on-chip components particularly the network-on-chip become increasingly prone to faults. Redundancy is the basic approach to fault tolerance and in this paper we investigate the hexagonal on-chip network topology with redundant diagonal inter-router links, having approximately 1.5 times the number of links as the mesh topology. To evaluate the fault tolerance of the hexagonal network with wormhole-switched routing, we present deadlock-free fault tolerant routing algorithms obtained by applying the turn model and without the use of costly virtual channels. To circumvent the problem of finding the right selection of turns to prevent deadlock, we propose an approach based on the transitive closure of the channel dependency matrix. The results indicate that the hexagonal NoC with the proposed adaptive routing algorithms significantly improves NoC resilience by being able to tolerate two router faults, while the mesh NoC can tolerate only one router fault. Moreover, the proposed approach is general and can be adopted for developing adaptive routing algorithms for any regular network topology.