CVF-coverification framework
Edelweis Helena Ache Garcez, Wolfgang Rosenstiel · Symposium on Integrated Circuits and Systems Design · 1998
Nowadays hardware/software codesign is consolidated as a research area However there is a lack of formal verification approaches, which are specially suitable to hardware and software. In this paper we present our coverification framework CVF, which consists of a system able to verify partitioned HW/SW systems using temporal logic model checking as a verification technique.