Bit-level systolic imlementation of 1-D and 2-D discrete wavelet transform
Swarnim Nayak · IEE Proceedings - Circuits Devices and Systems · 2005
The author presents a systolic array architecture for VLSI implementation of the one-dimensional discrete wavelet transform (DWT) which computes both high- and low-pass frequency coefficients in the same clock cycle. The architecture is simple, modular and cascadable for computation of one- or multidimensional DWTs. It needs 62% fewer registers than existing architecture, and the hardware utilisation of the proposed structure is very high. Two systolic architectures are presented for bit-level VLSI implementation of 1-D and 2-D DWT. Matrix transposition is avoided in the systolic architecture for bit-level VLSI implementation of 2-D DWTs.