Framework for design with LEON3 system and testing with SHA-1 algorithm
Madhulika Mohanty, Deepanjana Deb, Aravind Konidala, Ashish Mishra, Solomon Raju Kota · 2011
The performance of many frequently used, computationally extensive algorithms can be improved by implementing them in hardware. This paper presents a framework for interfacing IP cores for such algorithms with the LEON3 processor and integrating them with the open source GRLIB IP library. The framework has been implemented by designing an IP Core for SHA-1, which is a popular cryptographic hash function, and interfacing it with the AMBA Advanced Peripheral Bus of the LEON3 soft processor provided by GRLIB IP library. The entire framework has been tested on the Xilinx ML509-XUPV5 board.