On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits
Irith Pomeranz, Sudhakar M. Reddy · 2002
The first time unit where a fault in a synchronous sequential circuit is detected by a given test sequence T/sub 0/ is used by various procedures. One such procedure selects input sequences that are loaded onto an on-chip memory and used as seeds for built-in test pattern generation. Each input sequence is constructed based on a different fault f and is extracted from T/sub 0/ around the first detection time of f. In this work, we extend this procedure to consider multiple time units where every target fault f is detected by T/sub 0/ in order to select a shorter sequence based on f. The result is reduced storage requirements and test application time for this built-in test pattern generation approach.