FPGA implementation of the m-ary modular exponentiation
Anane Nadjia, Mohamed Anane · 2013
Modular exponentiation is a key operation of RSA cryptosystem and is very time consuming for large operands. It is performed using successive modular multiplications. This paper describes hardware architecture of the m-ary modular exponentiation with reduced number of Montgomery modular multiplications. This architecture has been implemented on FPGA circuit of Virtex-2 and presents best performances in terms of computation time and occupied resources.