An universal VLSI architecture for bit-parallel computation in GF(2/sup m/)
Chien-Ching Lin, Fu-Ke Chang, Hsie-Chia Chang, Chen‐Yi Lee · 2005
An universal VLSI architecture for bit-parallel computation in GF(2/sup m/) is presented. The proposed architecture is based on Montgomery multiplication algorithm, which is suitable for multiple class of GF(2/sup m/) with arbitrary field degree m. Due to the highly regular and modular property, our proposed universal architecture can meet VLSI design requirement. After implemented by 0.18/spl mu/m 1P6M process, our universal architecture can work successfully at 125MHz clock rate. For the finite field multiplier, the total gate count is 1.4K for GF(2/sup m/) with any irreducible polynomial of field degree m/spl les/8, whereas the inverse operation can be achieved by the control unit with gate count of 0.3K.