Chip design of a field programmable VLSI processor using memory-based cells
N. Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama · Society of Instrument and Control Engineers of Japan · 2003
This paper proposes a field programmable VLSI processor (FPVLSI) based on bit-serial architecture that makes the utilized ratio of hardware components in the cell very high irrespective of the word length. Based on the regular data flow of bit-serial architecture, a lookup table implemented using a shift register is proposed for the cell. One of the functional unit, memory unit and control unit can be implemented using the same cell. As a result, area of the cell is reduced. The FPVLSI with 64 cells is designed in a 0.18 /spl mu/m CMOS design rule. The performance of the FPVLSI is evaluated to be 13 times higher than that of the conventional FPGA in a typical application.