Flexible Signal Processing Platform Chip for Software Defined Radio with 103 GOPS Dynamic Reconf1gurable Logic Cores
Hisanori Fujisawa, Miyoshi Saito, Seiichi Nishijima, Naoki Odate, Yuki Sakai, Katsuhiro Yoda, Iwao Sugiyama, Teruo Ishihara, Yoshio Hirose, Hideki Yoshizawa · 2006
Software defined radio (SDR) is expected to be a progressive technology for wireless communications under multi-communication systems. SDR requires high performance, low power consumption, and short latency hardware. We have developed a single-chip baseband processing LSI for SDR based on a hybrid architecture of coarse-grain reconfigurable logic cores and flexible accelerator modules to achieve the required features. The maximum performance is 103 GOPS. Moreover, we implemented IEEE 802.11a and IEEE 802.11b, and show the effectiveness in latency.