An Embedded Hardware Architecture for Real-Time Super-Resolution in Infrared Cameras
Rodolfo Redlich, Luis Araneda, Antonio Saavedra, Miguel E. Figueroa · 2016
This paper presents a custom hardware architecture for fast, low-power super-resolution in infrared images. The architecture performs multiple-frame registration using the Lukas-Kanade optical flow algorithm with Gaussian pyramids, and uses a custom-designed reconstruction algorithm that generates a high-resolution image from multiple consecutive video frames with comparatively low computational cost. We show a prototype of the architecture running on a Xilinx Spartan-6 LX45 FPGA, which can scale a 160 × 120-pixel region of interest to 640 × 480 pixels using information from eight consecutive video frames. The circuit interfaces directly to the digital output of a FLIR Tau 2 infrared camera core and can process video at up to 150 frames per second while consuming 776mW of power.