NISAR: An AXI compliant on-chip NI architecture offering transaction reordering processing
Yang Xu, Zhang Qing-li, Fangfa Fu, Mingyan Yu, Cheng Liu · 2007
In this paper, we present an AXI compliant Network Interface (NI) for NoC, which can deal with the reordering problem and support the adaptive routing. On the basic of analyzing the necessity and feasibility of packet reordering, we propose a novel reordering mechanism based on look up table, which can guarantee globally ordering of the response transactions. Our NI (NISAR) also supports the master and slave core together. The average latency introduced by NISAR is 3-4 cycles, and the throughput achieves up to 0.87 flits/cycle for a random transaction length between 1 and 16. The proposed architecture synthesized with TSMC 0.13 um technology and the area of it is 0.28 mm2.