1.8mW, hybrid-pipelined H.264/AVC decoder for mobile devices
Sangkwon Na, Woong Hwangbo, Jae Moon Kim, Seunghan Lee, Chong‐Min Kyung · 2007
To meet the performance, area and power requirement constraints of H.264/AVC, we propose a hybrid pipeline architecture, and a data reuse mechanism to reduce off-chip memory access. A 4x4 sub-macroblock pipeline architecture is optimized for low power as well as performance. The proposed H.264/AVC decoder architecture can support CIF(352×288) 30fps videos at 6MHz with 1.8mW @ 1.65V, implemented in 0.18um technology.