LSI Architecture for VQ Systolic Array Systems
B. Tao, H. Abut, F. Mehran · 1986
We present an architecture for two high-speed, efficient processors to be used as elements in a systolic array for vector quantization (VQ). A distortion processor module (DPM) computes error terms at a rate of 10 million per second in a maximal pipeline configuration. Its structure is especially suited for highly concurrent processing such as in a systolic array system. An array processor controller (APC) administrates the system, receives distortion information from the array at a 10 MHz rate, and determines the optimum code either in a full-search or tree-search manner. The APC is programmable so that the same system is easily reconfigured for new applications. A real-time system was built and tested in a 0.5 bit per pixel (bpp) application, and produced no visible distortion and negligible SNR difference when compared to a floating-point simulation.