Efficient Implementation of Cache Coherence in Scalable Shared Memory Multiprocessors
Phanindra K. Mannava, Akhilesh Kumar, Laxmi Narayan Bhuyan · 2001
The cache coherence scheme for a scalable distributed shared memory multiprocessor should be efficient in terms of memory overhead for maintaining the directories, as well as network latency for a memory request. In this paper, we propose a cache coherence scheme which minimizes the memory access delay and at the same time, reduces the directory overhead by using a limited directory scheme. In the proposed scheme, pointer overflow is handled an efficient invalidation mechanism using logically embedded rings. rings for transmitting control messages. A single ring architecture for small scale multiprocessor and a multiple ring hierarchical architecture for a scalable multiprocessor are evaluated. In both the architectures, wormhole routing, in conjunction with the usage of ring, introduces a snoopy behavior to the proposed scheme. We will show, with the help of execution driven simulation results, that for several applications our techniques outperform the full map directory scheme, as well as the traditional implementations of limited directory schemes.