A Block Scaling FFT/IFFT Processor for WiMAX Applications
Yuan Chen, Yu-Wei Lin, Chen‐Yi Lee · 2006
This paper presents a low-power design of a two-stream MIMO FFT/IFFT processor for WiMAX applications. A novel block scaling method and a new ping-pong cache-memory architecture are proposed to reduce the power consumption and hardware cost. With these schemes, half the memory accesses and 64-Kbit memory can be saved. Furthermore, by proper scheduling of the two data streams, the proposed design achieves better hardware utilization and can process two 2048-point FFTs/IFFTs consecutively within 2052 cycles. A test chip of the proposed FFT/IFFT processor has been designed using UMC 0.13 mum 1P8M process with a core area of 1332times1590 mum2. The SQNR performance of the 2048-point FFT/IFFT is over 48 dB for QPSK and 16/64-QAM modulations. Power dissipation of two 2048-point FFT computations is about 17.26 mW at 22.86 MHz which meets the maximum throughput rate of WiMAX applications.