High throughput 2-D transform architectures for H.264 advanced video coders
Zhan-Yuan Cheng, Che‐Hong Chen, Bin-Da Liu, Jar‐Ferr Yang · 2005
In this work, high throughput hardware architectures for fast computation of the 2-D forward, inverse and Hadamard transforms suggested in H.264 advanced video coders (AVC) are presented. After complexity and efficiency analyses, we find that the proposed architectures could provide higher throughput rate and realize in a smaller chip area than the conventional row-column approaches. The proposed architectures are synthesized with TSMC 0.35 /spl mu/m technology. The synthesized multiple transform architecture could process 800 M samples/sec at 100 MHz for all the three transforms.