Superconducting Super Collider data compression and driver/modulator architecture
Bradly J. Cooke, K.S. Lackner, D.H. Sharp, C. L. Winter, Hans J. Ziock · Conference Record of the 1991 IEEE Nuclear Science Symposium and Medical Imaging Conference · 2002
Presents a prototype architecture that provides chip-level data compression and high-speed optical drive capabilities for rad-hard Super Collider data acquisition applications. The data compression is accomplished through a pipelined edge-detection and clustering algorithm, while the driver/modulator uses high-throughput data-management techniques, including variable register lengths, bus queuing, and time-division-multiplexing for fast optical-data transmission. An architecture of this sort can provide efficient transmission of a very large number of events. A practical 4*128 compressor architecture is introduced to illustrate the algorithm.>