FPGA implementation of fast adders using Quaternary Signed Digit number system
Reena Rani, Laxmi Kant Singh, Neelam Sharma · 2009
The limitation of speed of modern computers in performing the arithmetic operations such as addition, subtraction and multiplication suffer from carry propagation delay. Carry free arithmetic operations can be achieved using a higher radix number system such as Quaternary Signed Digit (QSD). We proposed fast adders based on Quaternary signed digit number system. In QSD, each digit can be represented by a number from -3 to 3. Carry free addition and other operations on a large number of digits such as 64, 128, or more can be implemented with constant delay and less complexity. The design of these circuits is carried out using FPGA tools. The designs are simulated using modelsim software and synthesized using Leonardo Spectrum.